It is well-known that the power network due to capacitive or inductive effect can cause some voltage drop at the contact points of the devices and the power network, and similarly voltage surge for ground network. The voltage drop or surge can cause increase of propagation delay of the device, therefore degrading the performance of VLSI circuit. Nowadays due to the scaling of devices, the voltage drop induced increase of delay has become increasingly important.
Traditionally, this voltage drop issue has been addressed in both timing simulation and timing analysis. In simulation a two-step approach is adopted, namely, simulation is carried out first without power network and record the current at the contact points between devices and power network, secondly feed the currents at the contact points to the power network and perform a detailed simulation on the power network without the devices based on the limited set of vectors to obtain voltages of the power network nodes accurately and report voltage drops at those contact points and currents along the wires. However, if the worst case of the voltage drop for each of the gates is used to re-simulate the circuit, the result can be too pessimistic.
Another method to tackle the voltage drop issue is to use vector-less or timing analysis approach in which the critical paths can be identified. Kriplani et al. have proposed iMax algorithm which makes use of timing analysis to generate a timing window or the so-called uncertainty interval in which the gate can switch with power current associated with the switching. With all the possible switching during the uncertainty interval, the maximum envelope current (MEC) waveform for each gate is built up. At any point of time of the MEC waveform the current is maximum from all possible switching of the gate. The voltage drop is then calculated by using the MEC and the power network. This method can provide very pessimistic result. Bai et al. have improved the result by taking into account of functional dependences and have formulated this into an optimization problem to maximize the voltage drop by expressing voltage at bus nodes in terms of gate currents. Bai et al. also have proposed an approach utilizing a specified path in static timing analysis and get the current for each gate along this path, then figure out the voltage drop for this gate and re-calculate the gate delay based on the new supply voltage which can be different for different for the gates along the same path. The new path delay finally is achieved by summing all the new gate delays. This method is more realistic than the previous ones in the sense that the uncertain interval of the gate along the path is small, because we only limit the signal propagation along this path only. However, how to calculate accurate current for each gate accurately can be a very challenging problem.
The aforementioned method utilizing the specified path as provided by timing analysis looks promising, still there are some shortcomings which need to be overcome. In calculating voltage drop for one gate along the specified path the main difficulty lies in the fact how to choose the other gates with their switching overlapping with the switching of this gate along the path and include all the switching currents. By adopting functional dependency in the design, the whole path needs to be considered. For example, the rise or fall on the nodes along the path and some logic value, which may be VDD, GND, rise, or fall at the side inputs of the gates along the path need to considered explicitly in order to generate more sensible results. Besides, the circuit most likely contains multi-phase sequential elements. The node may store several delays times with respect to different clock phases which need to be considered in determining the overlapping of switching of gates. Furthermore, to increase accuracy the modeling part can be improved. The switching current for each gate or sequential element must be modeled using polynomial fit. The cell in ASIC design may contain several gates and the switching current need to be modeled by several triangles. By knowing these switching current for the gates, a delay calculator is used to calculate voltage drop and new updated path delay is followed accordingly, and more accurate critical path analysis is achieved. To accurately carry out critical path analysis including set up time and hold time checks, clock skew, set up time, and clock to output delay also need to be re-evaluated by considering voltage drop effect. In the clock skew analysis interconnect delay plays a pivotal role and for ASIC design the effective capacitance should be adopted.